1. Field of the Invention
This invention relates to spatial light modulators (SLMs), and more particularly to a micro mirror structure with hidden cross-members to maximize pixel fill ratio, minimize scattering and diffraction, and achieve a high contrast ratio and high image quality.
2. Background
Spatial light modulators (SLMs) have numerous applications in the areas of optical information processing, projection displays, video and graphics monitors, televisions, and electrophotographic printing. Reflective SLMs are devices that modulate incident light in a spatial pattern to reflect an image corresponding to an electrical or optical input. The incident light may be modulated in phase, intensity, polarization, or deflection direction. A reflective SLM is typically comprised of an area or two dimensional array of addressable picture elements (pixels) capable of reflecting incident light. A key parameter of SLMs, especially in display applications, is the ratio of the optically active area to the pixel area, also called the “fill ratio.” A high fill ratio is desirable.
Prior art SLMs have various drawbacks. The drawbacks include, but are not limited to: (1) a lower than optimal optically active area that reduces optical efficiency; (2) diffraction and scattering that lowers the contrast ratio of the display; (3) reliance upon materials that have long-term reliability problems; and (4) complex manufacturing processes that increase the expense of the device and lower the yield of devices from a wafer.
Many prior art devices include substantial non-reflective areas on their surfaces. This provides low fill ratios, and provides lower than optimum reflective efficiency. For example, U.S. Pat. No. 4,229,732 discloses MOSFET devices that are formed on the surface of a device in addition to mirrors. These MOSFET devices take up surface area, reducing the fraction of the device area that is optically active and reducing reflective efficiency. The MOSFET devices on the surface of the device also diffract incident light, which lowers the contrast ratio of the display. Further, intense light striking exposed MOSFET devices interfere with the proper operation of the devices, both by charging the MOSFET devices and overheating the circuitry.
Similarly, many devices include walls or frames that surround each micro mirror and separate adjacent mirrors, as shown in FIG. 3A. These walls may be used to support the mirror cross-member, and often extend to a height coplanar with the micro mirror. The presence of the walls limit mirror size and thus limit the fill ratio possible using such designs.
Some SLM designs have rough surfaces that scatter incident light and an aluminum film deposited on an low-pressure chemical vapor deposition (LPCVD) silicon nitride layer. It is difficult to control the smoothness of these reflective mirror surfaces as they are deposited with thin films. Thus, the final product has rough surfaces, which reduce the reflective efficiency.
Another problem that reduces reflective efficiency with some SLM designs, particularly in some top hanging mirror designs, is large exposed cross-member surface areas. These exposed cross-member surface areas result in scattering and diffraction due to the cross-member structure, which negatively impacts contrast ratio, among other parameters.
Many conventional SLMs, such as the SLM disclosed in U.S. Pat. No. 4,566,935, have cross-members made of aluminum alloy. Aluminum, as well as other metals, is susceptible to fatigue and plastic deformation, which can lead to long-term reliability problems. Also, aluminum is susceptible to cell “memory,” which means that the rest position begins to tilt towards its most frequently occupied position.
Other conventional SLMs require multiple layers and processing steps. Manufacturing such a multi-layer SLM requires use of repetitive multi-layer thin film stacking, etching, and other processes that increase the expense and complexity of manufacturing the device. Often, the use of these techniques also produces lower yields. For example, use of these techniques of inexpensive depositions of multiple layers, depositions and removals of sacrificial materials, epitaxial growth steps, and multiple etching and stripping steps. In addition, some flip-and-bond processes require meticulous alignment of the various layers.
Conventionally, some SLMs also require the use of silicon on insulator (SOI) wafers. In addition to driving up the cost of SLM manufacturing, the use of SOI wafers requires that they be thinned using chemical mechanical planarization (CMP), which may cause the wafer to break or delaminate, and often causes the highest yield loss of all SLM processing steps.
What is desired is an SLM with improved reflective efficiency, SLM device long-term reliability, and simplified manufacturing processes.